A clamp protection circuit, that is, a circuit used to protect a part of the circuit from exceeding a clamp value, so as to maintain the circuit operating safely and moreover, the device and function of the circuit won't be damaged. Such voltage clamp protection circuit is widely applied in an integrated circuit design, especially in a power supply controller IC, such as AC-DC converter, power factor correction controller and so on.
Zero-crossing detection module is widely used in Transition Mode Power Factor Correction (PFC) controller chip for detection of zero current crossing event in boost inductor. When the zero current crossing event is detected, a new switch cycle is triggered by turning on power switch. Thus, the system operates at the boundary between continuous and discontinuous current mode or so called Transition Mode. Switching loss and noise can be minimized while the system operates in Transition Mode. Zero-crossing detection function is normally realized by inspecting the voltage change of the secondary side of the transformer depicted in FIG. 1. The operation principle of zero-crossing
detection is described as follows: When the power switch device Q is conducted, the inductor Lb is charged by the rectified AC voltage Vg(t), the diode D at the output terminal is reverse biased, and the load current is obtained from the output capacitor Co, the current of the inductor Lb is linearly increased, and the voltage of Vz is −Vg(t)/n where n is the turn ratio of the transformer. As the RMS value of the AC input voltage is in the range of 85 V to 265 V, the voltage variation of Vz is confined from minus a ten of to a few tens of volts. If such Vz is directly added to the ZCD pin of the PFC controller chip, high voltage stress sustainable device is required, which in turn increases the die size and complicates the circuit design. In order to release the high voltage stress constrain, a clamp protection circuit is introduced.
A prior art voltage clamp design is illustrated at the circuit 100 in FIG. 1. When the voltage of Vz is negative, the isolation high voltage device 106 is conducted, and the gate voltage of device 104 is pulled down, and branch current I1 is generated. The branch current I1 is mirror amplified by a high voltage device 105 to form a branch current I2. The branch current I1 and I2 are combined to have a lower limit clamp current I which goes through the resistor R1 to clamp the voltage of ZCD pin to the voltage of NodeA−Vgs(106), so as not to damage the devices in the chip. However, there is a substantial voltage change for Vz from application to application, and the lower limit clamp current I can vary from few tens μA all the way up to several mA. Therefore, an external high voltage power source Vcc is required for the voltage clamp circuit working properly. FIG. 1 illustrates a prior art circuit design for voltage clamp. In order to work with high voltage power source Vcc, high voltage device 101, 104, 105 and 106 are used that occupies large silicon area and results in high cost. In addition, as the device 101, 104, 105 are voltage-controlled, the accuracy of the clamp voltage of the clamp protection circuit is very limited while the variation of bias current, process and temperature are taken into account. Meanwhile, device 105 is vulnerable to ESD damage as it forms an electrostatic discharge path between the ZCD pin and power supply Vcc. The damage of device 105 will cause the voltage clamp circuit malfunction.
Accordingly, a clamp protection circuit with improved precision of the clamp voltage, simplified design and silicon area saving is proposed.